* Two DMA slots are now exported for the external peripherals
* A dummy example of an FIFO peripheral using RX/TX streaming windows is added

…main

* Replace the IFFIFO window interface by plain status/control registers
* Add acceleration feature in IFFIFO
* Adapt software example
* Rename exported DMA slots

* fifo_v3 replaced by prim_fifo_sync
* the example features use of valid/ready signals

* Implement status register (empty/available/full/watermark)
* Implement interrupts (available/watermark/full) [untested]

- add iffifo interrupt into the PLIC system
- remove FULL and AVAILABLE interrupts as they can be implemented with REACHED interrupts

* Populate pointer, increment and slot registers for broadcasting
* Remove code duplicate
* Initialize registers
* Add EOF new line

* Add symbols
* Add broadcast target

merge origin into dma-broadcast via main